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Papers at IEDM 2020 Explore Ways to Leverage 3D Technology's Strengths For Lowering Device Energy Consumption and Energy Lost in Data Transmission
Today, storage-class memories like high-density 3D crossbar RRAM are promising for applications requiring a large amount of on-chip memory, explained the paper 3D RRAMs with Gate-All-Around (GAA) Stacked Nanosheet Transistors for In-Memory-Computing. RRAM is a leading candidate due to its high density, good scalability, low operating voltage, and easy integration with CMOS devices. Another attractive aspect of RRAM is their ability to perform primitive Boolean logic operations for in-memory and neuromorphic computing. However, if the 1T1R design is the most reliable architecture for IMC, the cell size remains limited by the conventional access transistor.
The team showed that by using extensive characterization at the array level, conductance relaxation after MLC programming is the limiting factor for storage applications, rather than device-to-device or cycle-to-cycle variations," said Eduardo Esmanhotto, an author of the paper. This phenomenon limits storage to 2-bit per RRAM for such applications. Conversely, neural network inference is resilient to relaxation and therefore it is advantageous to program nine levels per RRAM, equivalent to 3.17 bits.
CEA is a French government-funded technological research organisation in four main areas: low-carbon energies, defense and security, information technologies and health technologies. A prominent player in the European Research Area, it is involved in setting up collaborative projects with many partners around the world.