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Published on 7 December 2023
Research FieldMaterials and applications

Domaine-SMaterials and applications

ThemeEngineering sciences

Theme-SEngineering sciences

Materials and applications Engineering sciences Materials and applications Engineering sciences DRT DPFT SSURF LSJ Grenoble
Selective removal of metal alloy for advanced silicidation applied to sub-20nm CMOS transistors
CMOS transistor performances depend on electrical contact resistivity reduction. Thus, self aligned silicidation (salicide) is one of the key processes which have to be improved to meet the ITRS requirements for the future technological nodes. Nowadays, solid state reaction between thin metal layer (Ni1-yPty < 10nm) and a silicon substrate allows to decrease access resistances of transistor source & drain. The metal is currently deposited by physical vapor deposition method all over the wafer surface. Under heat treatment, metal reacts preferably with semiconductor areas rather than dielectrics ones. Then, unreacted metal layer is selectively etched with an appropriate acidic solution; only metal silicide remains.As new specifications (use of ultra-thin Ni-alloy,very low temperature process leading to partial salicidation, use of various additive metals ...)are required for advanced nodes (C20nm & C14nm), the capability to chemically remove the excess of metal on dielectric areas has to be investigated. In the clean room environment of CEA-LETI (Grenoble, France), the candidate will work on innovative wet chemistries to remove selectively the different metallic layers (Ni, Pd, NiCo, NiPd…). In a first time preliminary test will be conducted on sample in manual tank in order to check removal kinetic and global selectivity on structures devices… Based on several characterization techniques (TXRF, XRR, AFM, SEM, TEM, XRD…), residual additive interaction with dielectric and chemical mixture behavior towards the metal rich phase on silicided area (roughness, resistivity) will be studied. Different semi-conductor (Si, SiGe…) and dielectrics surfaces (SiO2, SixNy…) will be investigated. Afterwards the most promising selective processes will be selected to be installed on a fully automatic 300mm tool. Finally, best processes will be integrated on critical patterned wafer architectures for morphological and electrical characterizations.
Département des Plateformes Technologiques (LETI) Service des procédés de Surfaces et Interfaces Laboratoire
LOUP Virginie CEA DRT/DTSI/SSURF CEA-LETI, MINATEC Campus, DTSI/SSURF 17 rue des Martyrs - 38054 Grenoble Cedex 9 Bat. 41.25 Pièce 312 04 38 78 10 65
Start date1/10/2012

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