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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Published on 29 March 2018
Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization
Description
 
Date 
Authors
Doria R.T., Trevisoli R., de Souza M., Barraud S., Vinet M., Faynot O., Pavanello M.A.
Year2017-0295
Source-TitleMicroelectronic Engineering
Affiliations
Department of Electrical Engineering, Centro Universitário FEI, Av. Humberto de Alencar Castelo Branco, 3972, Sao Bernardo do Campo, Brazil, LETI, Commissariat à l'Energie Atomique et aux Energies Alternatives, 68B Avenue des Martyrs, Grenoble, France
Abstract
This work presents, for the first time, an experimental analysis of the low-frequency noise and the effective trap density dependence of junctionless nanowire transistors (JNTs) on the substrate bias. The study has been performed for devices with different channel lengths and doping concentrations biased close to the threshold and deep in linear regime. It has been shown that the surface potential of JNTs is strongly influenced by the substrate bias even above threshold. Thus, the drain current noise spectral density and the effective trap density can be improved or degraded depending on the bias applied to the substrate of the devices. Additionally, it is shown that, the variation on the substrate bias enables the evaluation of traps with different activation energy ranges, which is more evident in heavier doped devices due to the higher threshold voltage sensitivity to the substrate bias. © 2017 Elsevier B.V.
Author-Keywords
Effective trap density, Junctionless nanowire transistors, Low-frequency noise, Substrate bias
Index-Keywords
Activation energy, Drain current, Nanowires, Sensitivity analysis, Spectral density, Spurious signal noise, Thermal noise, Threshold voltage, Doping concentration, Experimental analysis, Interface trapped charges, Low-Frequency Noise, Nanowire transistors, Substrate bias, Substrate bias effects, Trap density, Interfaces (materials)
ISSN1679317
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