Global demand on semiconductor solutions (device, circuit, system) has skyrocketed during the last few years, especially in reliation with COVID worldwide crisis. This industry has revealed its significance in the present world has well as its weaknesses. The European council decided to launch an ambisious program called 'Chip Act' to develop a solid semiconductor european industries network based on its champions such as ST microelectronics, SOITEC and the CEA-LETI. In France, the french government decided to push forward the FDSOI technology using the CEA-LETI to develop the 10nm node and beyond. The reach the MOSFET expected performance of such an aggressive node, several original technological solutions are considered, such as the use of Si-channel stressors to boost the mobility and the ON state current or the use of thinned Si channel film and gate oxide. The influence of these novel processes and technological bricks on MOSFET FoM and reliability must be carefully studied before entering in a production mode. The PhD student will address the electrical characterization of the High-k/Metal Gate stacks (initial performance) and their long term reliability (aging under stress). Electrical modeling of the experimental data will be used to determine the crucial parameters to improve and give quick feedback to the Device development Lab.